1    package com.simplifide.scala2.test.language 
2     
3    import com.simplifide.generate.generator.CodeWriter 
4    import com.simplifide.generate.signal._ 
5    import com.simplifide.generate.blocks.basic.flop.ClockControl 
6    import com.simplifide.generate.language.Conversions._ 
7    import com.simplifide.generate.parser.model.{SignalType, Expression} 
8    import com.simplifide.generate.hier2.Entity 
9    import com.simplifide.generate.TestConstants 
10   import com.simplifide.generate.project2.{Project, Module} 
11   import com.simplifide.generate.signalproc.Filter 
12   import com.simplifide.generate.signal.Constant._ 
13   import com.simplifide.generate.test.Test._ 
14   import com.simplifide.generate.test.{Test, Isim, TestModule} 
15    
16   /** 
17    * This test case is a simple example of an iir filter. It contains all of the classes required to build and test 
18    * this module. The code containing the actual operation of a fully parameterizable filter is only about 10 lines of 
19    * code. 
20    * 
21    * The design files can be found at       http://scaladl.com/examples/iir/design  
22    * The test files can be found at         http://scaladl.com/examples/iir/test/  
23    * The html documentation can be found at http://scaladl.com/examples/iir/doc/ 
24    * 
25    */ 
26    
27   class IirTest { 
28    
29   } 
30    
31   object IirTest { 
32    
33     /** Project which contains a simple IIR */ 
34     object IirProject extends Project { 
35       // Location where the project is created 
36       val location:String = TestConstants.locationPrefix + "language" + TestConstants.separator + "iir_output" 
37    
38       // Clock used for the design 
39       implicit val clk         = ClockControl("clk","reset") 
40       // Number of Filter Taps 
41       val len = 3 
42       // Array of Signals used for the numerator taps 
43       val num             = array("num",INPUT,S(8,6))(len) 
44       // Array of Signals used for the denominator taps 
45       val den             = array("den",INPUT,S(8,6))(len) 
46       // Input Output Signals 
47       val x              = signal("signal_in1",INPUT,S(8,6)) 
48       val z              = signal("signal_out",OUTPUT,S(8,6)) 
49       // Internal Width 
50       val iW = S(12,8) 
51       // Top Level Module for the Design 
52       override val root = new IirEntity("iir",num,den,x,z,iW) 
53       // List of Test Cases 
54       override val tests    = List(Test(new TestCase(root))) 
55       // Type of Test -- For this case ISIM 
56       override val testType = Some(new Isim(this)) 
57     } 
58    
59     /** Entity for the IIR */ 
60     class IirEntity(name:String, 
61             val a:SignalTrait, 
62             val b:SignalTrait, 
63             val x:SignalTrait, 
64             val z:SignalTrait, 
65             val iW:FixedType)(implicit clk:ClockControl) extends Entity.Root(name,name)(clk) { 
66       // Input Output Signals 
67       override val signals = clk.allSignals(INPUT) ::: List(a,b,x,z) 
68       // Function which creates a module 
69       override val createModule = new IIR(this,iW).createModule 
70     } 
71    
72     /** Generic IIR Implementation */ 
73     class IIR(entity:IirEntity, 
74             val iW:FixedType)(implicit clk:ClockControl) extends Module(entity.name) { 
75    
76       // Import the signals from the entity 
77       import entity._ 
78       val n = clk                   // Assign the clk to n for convenience 
79       val len = a.numberOfChildren  // Number of Taps for the filter 
80       // Internal Signal Declarations 
81       val internal     = signal("internal_sig",WIRE,iW) 
82       val internal_out = signal("internal_out",WIRE,z.fixed) 
83       val y            = register(internal)(len-1) 
84       // Feedback Taps 
85       y(n) := x(n)    + List.tabulate(len)(i => RC(a(i)*y(n-i-1))).reduceLeft[Expression](_+_) 
86       // Feed-forward Taps 
87       internal_out(n) := List.tabulate(len)(i => RC(b(i)*y(n-i-1))).reduceLeft[Expression](_+_) 
88       // Output Assignment 
89       z := internal_out 
90    
91     } 
92     /** Test Case for the Filter */ 
93     class TestCase(val entity:IirEntity)(implicit clk:ClockControl) extends TestModule("test_iir",entity) { 
94       // Tap Values for numerator and denominator 
95       val num = List(.3,.58,.3) 
96       val den = List(0.0,.17,0.0) 
97       // Input values currently a sine wave 
98       val inputs:List[Double] = List.tabulate(length + 3)(x => math.sin(x.toDouble/64.0)) 
99       val outputs = inputs.map(x => Constant(x,entity.z.fixed)) 
100      // Test Assignment to the numerator and the denominator 
101      num.zipWithIndex.foreach(x => entity.a(x._2) --> x._1) 
102      den.zipWithIndex.foreach(x => entity.b(x._2) --> x._1) 
103      entity.x           --> (inputs.map(Constant(_)))        // Assign the System Input 
104      entity.z           <-- (outputs,3,length+3,4)           // Check the System Output 
105   
106      this.createTest 
107    } 
108   
109    def main(args:Array[String]) = { 
110      IirProject.createProject2 
111    } 
112  }