1    package com.simplifide.scala2.test.language 
2     
3    import com.simplifide.generate.generator.CodeWriter 
4    import com.simplifide.generate.signal._ 
5    import com.simplifide.generate.blocks.basic.flop.ClockControl 
6    import com.simplifide.generate.parser.block.state.StateModel._ 
7    import com.simplifide.generate.parser.block.state.{State, StateModel} 
8    import com.simplifide.generate.parser.RegisterMapHolder 
9    import com.simplifide.generate.blocks.proc.{ProcessorBus, Address, RegisterMap} 
10   import com.simplifide.generate.language.Conversions._ 
11   import com.simplifide.generate.hier2.Entity 
12   import com.simplifide.generate.TestConstants 
13   import com.simplifide.generate.project2.{Project, Module} 
14    
15   /** 
16    * This test case is for a processor simple processor interface. The advantage of this code is that all of the information 
17    * is stored in the same place so that both the verilog code, documentation, and software interfaces can be automatically 
18    * generated. 
19    * 
20    * The design files can be found at      http://scaladl.com/examples/proc/design/

21    * The test files can be found at        http://scaladl.com/examples/proc/test/

22    * The html documentation can be found athttp://scaladl.com/examples/proc/doc/

23    * 
24    */ 
25    
26   class ProcessorInterfaceTest { 
27    
28   } 
29    
30   // TODO Convert the Processor Interface to the entity to allow outputs to be added to the entity 
31   object ProcessorInterfaceTest { 
32    
33     /** Top Level Project which contains the processor interface */ 
34     object Proj extends Project { 
35       // Sets the location where the projects outputs will be stored 
36       val location:String = TestConstants.locationPrefix + "outputs" + TestConstants.separator + "proc" 
37       // Create the clock for the design 
38       implicit val clk = ClockControl("clk","reset") 
39       // Set the Top Level Module for the design 
40       override val root = new Ent() 
41     } 
42    
43     class Ent()(implicit clk:ClockControl) extends Entity.Root("processor_interface","processor_interface") { 
44       // Creates a bus which contains the signal required for the processor interface 
45       val processorBus = ProcessorBus(clk, 
46         SignalTrait("wrAddress",INPUT,U(3,0)), 
47         SignalTrait("wrValid",INPUT,U(1,0)), 
48         SignalTrait("wrData",INPUT,U(32,0)), 
49         SignalTrait("rdAddress",INPUT,U(3,0)), 
50         SignalTrait("rdValid",INPUT,U(1,0)), 
51         SignalTrait("rdData",OUTPUT,U(32,0))) 
52       // Set the signals for this entity 
53       override val signals = clk.allSignals(INPUT) ::: processorBus.signals 
54       // Create the module associated with this entity 
55       override def createModule = new Mod(this).createModule 
56    
57     } 
58    
59     class Mod(entity:Ent)(implicit clk:ClockControl) extends Module("processor_interface") with RegisterMapHolder { 
60         // Import all of the internal values from the entity 
61         import entity._ 
62    
63         val processorBus = entity.processorBus 
64    
65         sRegister(0,0 ,"a", 32) -- "Test Register" 
66         sRegister(1,0 ,"b", 32) -- <p>Html Documentation <i>Test</i></p> 
67         sRegister(2,0 ,"c", 16) -- "Test Register" 
68         sRegister(2,16,"d", 16) -- "Test Register" 
69    
70         //entity.appendSignals(this.createRegisterSignals) 
71         this.processor_interface(this) 
72    
73     } 
74    
75    
76    
77    
78    
79     def main(args:Array[String]) = { 
80        Proj.createProject2 
81     } 
82   }