1    package com.simplifide.scala2.test.language 
2     
3    import com.simplifide.generate.project2.{Module, Project} 
4    import com.simplifide.generate.blocks.basic.flop.ClockControl 
5    import com.simplifide.generate.signal.complex.ComplexSignal 
6    import com.simplifide.generate.language.Conversions._ 
7    import com.simplifide.generate.parameter.{ModuleScope, Parameter} 
8    import com.simplifide.generate.hier2.Entity 
9    import com.simplifide.scala2.test.language.HierarchyTest.RootA 
10   import com.simplifide.generate.signal._ 
11   import com.simplifide.generate.parser.model.SignalType 
12   import com.simplifide.generate.TestConstants 
13   import com.simplifide.generate.test.Test._ 
14   import com.simplifide.generate.test.{Test, TestModule, Isim} 
15    
16   /** 
17    * This test case gives an example of how the hierarchy is designed. Module connections are automatically handled 
18    * by name with a method to override the naming convention. The approach is similar to emacs autoargs 
19    * 
20    * The design files can be found at      http://scaladl.com/examples/hier/design/

21    * The test files can be found at        http://scaladl.com/examples/hier/test/

22    * The html documentation can be found athttp://scaladl.com/examples/hier/doc/

23    * 
24    */ 
25    
26    
27   /** FFT Project class which contains the list of modules and file locations */ 
28   class HierarchyTest extends Project { 
29     // Clock which is used for the design. 
30     implicit val clk = ClockControl("clk","reset") 
31     // Project Location of the design 
32     val location:String = TestConstants.locationPrefix + "outputs" + TestConstants.separator + "hier" 
33     // Top Level Module for the Design 
34     override val root     = new RootA() 
35     // Defines the Tests for this project 
36     override val tests    = List(Test(new HierarchyTest.TestCase(root))) 
37     // Selects the simulator for this module - ISIM for this case 
38     override val testType = Some(new Isim(this)) 
39   } 
40    
41   object HierarchyTest { 
42     // Clock which is used for the design. 
43     implicit val clk = ClockControl("clk","reset") 
44    
45     /** Root Module of the Design */ 
46     class RootA extends Entity.Root("rootA","rootA") { 
47       // Definition of an instance for this module 
48       val branchA = new BranchA() 
49       // List of Instances in this module 
50       override val entities = List(branchA) 
51     } 
52    
53     /** Sub-block of the Root Module */ 
54     class BranchA extends Entity.Branch("branchA","branchA") { 
55       // Creation of Leaf Modules 
56       val leafA = new LeafA(this) 
57       val leafB = new LeafB(this) 
58       // List of Instances in the design 
59       override val entities = List(leafA,leafB) 
60     } 
61    
62     // Example Leaf Module 
63     class LeafA(val parent:BranchA)(implicit clk:ClockControl) extends Entity.Leaf("leafA","leafA") { 
64       // Input and Output Signals Defined 
65       val modInput  = Bus("a_in",TestBus) 
66       val modOutput = Bus("b_in",TestBus.reverseType) // Reverse Type reverses the direction of this output 
67       // List of Signals in this entity 
68       override val signals = clk.allSignals(INPUT) ::: List(modInput,modOutput) 
69     } 
70    
71     // Example Leaf Module 
72     class LeafB(val parent:BranchA)(implicit clk:ClockControl) extends Entity.Leaf("leafB","leafB") { 
73       // Output of this Module 
74       val modOutput = Bus("b_out",TestBus.reverseType) 
75       // List of Signals in the Design. The output of LeafA is included which will be automatically connected 
76       override val signals = clk.allSignals(INPUT) ::: List(parent.leafA.modOutput.reverseType,modOutput) 
77     } 
78    
79         /** Test Case for the State Machine */ 
80     class TestCase(val entity:RootA)(implicit clk:ClockControl) extends TestModule("state_test",entity) { 
81       // Run the condition which controls the state machine like a counter 
82       this.createTest 
83     } 
84    
85    
86    
87     /** Bus which is used in this design for signal connections */ 
88     object TestBus extends BusType { 
89       override val signals:List[SignalTrait] = 
90           List(SignalTrait("rdy",OpType.Output), 
91                SignalTrait("data",OpType.Input), 
92                SignalTrait("vld",OpType.Input)) 
93     } 
94    
95    
96     def main(args:Array[String]) = { 
97       val test = new HierarchyTest() 
98       test.createProject2 
99     } 
100   
101   
102   
103   
104  } 
105   
106